1. Field of the Invention
The present invention relates to semiconductor memories, and in particular, to organization and layout thereof.
2. Description of the Related Art
In the sub-micron regime of semiconductor lithographic processes, the proximity of adjacent features can have a profound effect on the size and shape of a given feature. A very noticeable effect occurs, for example, in the channel length of a metal-oxide-silicon transistor (i.e., MOS transistor), depending on the spacing to the neighboring polysilicon (i.e. "poly") feature.
In the design of SRAM circuits, it is desirable to have the smallest physical cell possible. An example of a six-transistor memory cell memory cell 10 is shown in FIG. 1. Such a memory cell is useful for static memory arrays such as, for example, cache memories, first-in-first-out buffers (FIFOs) and stand-alone static random access memories (SRAMs). The memory cell 10 includes a pair of cross-coupled N-channel transistors 15, 16 coupling a complementary pair of internal nodes 17, 18 to ground. A pair of cross-coupled P-channel transistors 13, 14 couple the internal nodes 17, 18 to an upper power supply voltage, such as VDD. As shown in FIG. 1, an isolated array power supply VDDMX (i.e., "VDD matrix") may be employed which is separate from the VDD used in other sections of an integrated circuit containing such an array of memory cells. Together, the pair of cross-coupled N-channel transistors 15, 16 and the pair of cross-coupled P-channel transistors 13, 14 form a static flip-flop, which is read and written by way of two N-channel access transistors 11, 12 which respectively couple internal nodes 17, 18 to true and complement bit lines 19, 20 when its word line 21 is selected and driven high.
One of the challenges in making a small SRAM cell is that of cell stability. That is, it must be possible to read the data from the cell without disturbing the data stored in the cell. One of the critical factors in determining cell stability is often referred to as the "Beta" ratio. This is generally thought of as the conductance ratio of the pulldown transistors (transistors 15 and 16) to that of the access transistors (transistors 11 and 12). For the transistor sizing shown in FIG. 1, such a Beta ratio is equal to [(W/L of pulldown transistor).div.(W/L of access transistor)]=[(1.0/0.4).div.(0.7/0.4)]=1.43. The larger the Beta ratio (large pulldown transistors and small access transistors) the more stable the cell.
An additional factor which is crucial to the cell stability is any difference in channel length between the pulldown transistors (transistors 15 and 16), the P-channel pullup transistors (transistors 13 and 14), or the access transistors (transistors 11 and 12). The memory cells at the very edge of an array are susceptible to such variation in channel length due to the lithographic proximity effects already noted. In effect, the transistors on the outside edge of the outermost memory cells (both the last row and the last column of the array) will have gate lengths (as well as other attributes) that are different than the transistors on the inside edge of these cells. These effects contribute to a degradation of the cell stability because the variations in channel length (and other attributes) induce differential offsets in the cell.
To reduce these undesirable edge effects, it is common to add non-functional sacrificial rows and columns of otherwise identical or nearly identical memory cells around the periphery of a memory array. The "word lines" of such sacrificial rows of memory cells are frequently grounded (i.e., connected to the lower power supply, VSS), and the "bit lines" of such sacrificial columns of memory cells are frequently connected to the upper power supply (e.g., VDD). By adding these sacrificial cells, all of the data-storing cells in the array (including those at the edges of the array) are contained in a lithographically homogeneous environment. Consequently, variations in channel length and other attributes are reduced, and memory cell stability is enhanced. However, these sacrificial "guard" cells add to the array area without increasing the storage capacity of the array. Improved techniques for reducing these memory array edge effects are desirable.